1. Field of the Invention
The present invention relates to a signal detection apparatus, especially to a signal detection apparatus utilizing a fast/multi-frequency clock generator to generate a sampling clock signal.
2. Description of the Prior Art
The protocol for transmitting data between electronic apparatuses is always a key point in research and development. There are various protocol standards for transmitting a large amount of data in high speed, e.g. integrated drive electronics (IDE), advanced technology attachment (ATA), serial ATA (SATA), and so on. SATA is the improved version of ATA.
Referring to FIG. 1(a) and FIG. 1(b), FIG. 1(a) is a schematic diagram of two electronic apparatuses 10 and 12 transmitting data between each other based on SATA standard. FIG. 1(b) is a waveform diagram of a set of signals 22 of SATA of the prior art. As shown in FIG. 1(a), the electronic apparatus 10 connects to the electronic apparatus 12 by two wirings 14 and 16 in the SATA standard. Each of the electronic apparatuses 10 and 12 has a transmitting side 18 and a receiving side 20. The transmitting side 18 of the electronic apparatus 10 connects to the receiving side 20 of the electronic apparatus 12 by the wiring 14. The receiving side 20 of the electronic apparatus 10 connects to the transmitting side 18 of the electronic apparatus 12 by the wiring 16.
The waveform diagram shown in FIG. 1(b) represents a set of SATA signals 22. According to the SATA protocol, the set of signals is used for building a channel of communication to transmit data. Under the SATA protocol, the two electronic apparatuses, which transmit data between each other, respectively represent a host and a device.
For example, when the electronic apparatus 10 is the host, and it transmits data to the device, which represents the electronic apparatus 12, a set of out of band (OOB) signals 22 is sent out to build the connection to transmit data. The set of OOB signals 22 includes a COMRESET/COMINIT signal, and a COMWAKE signal for ensuring that connection between the two electronic apparatuses 10 and 12 is being built. After the electronic apparatuses 10 and 12 respectively receive a device align signal and a host align signal, the connection between host and device is established, and then the electronic apparatuses 10 and 12 start to transmit data. The electronic apparatus 10 and the electronic apparatus 12 respectively have a determination circuit (not shown) for determining whether the signal transmitted via the wirings 14 and 16 is a COMRESET signal, a COMINIT signal, or a COMWAKE.
Referring to FIG. 2, FIG. 2 is a schematic diagram for representing the waveform of the COMRESET signal, the COMINIT signal, and the COMWAKE signal. In general, these signals have a first state and a second state. The first state represents an idle state, and the second state represents a burst state. The time interval of the first state depends on different signals, as shown in FIG. 2.
The determination circuit detects the input signal in a sampling manner. The determination circuit first receives a clock signal from a clock generator. According to the received clock signal, the determination circuit samples the input signal by a specific time interval and compares the sampled input with that of processing the COMRESET signal, the COMINIT signal, or the COMWAKE signal to obtain a detection result.
However, the electronic apparatus 10 or the electronic apparatus 12 may get into an idle state sometimes due to the demand of the system. When the apparatus is in the idle state, the clock generator of the apparatus may turn off, so the determination circuit cannot obtain the clock signal. When the apparatus gets into the idle state, the prior art utilizes a set of RC circuits to detect the input signal. However, due to the variation in production processes, the time parameter of the RC circuit usually varies, and the detection result will be inaccurate.